1. Field of the Invention
The present invention relates generally to the design of buffers providing constant voltage, and also to its application in the design and implementation of a multi-stage ADC.
2. Related Art
Constant reference voltages are needed in several environments. An example of such environment in which analog to digital converters (ADC) are used. An ADC refers to a component which receives an analog signal as input and provides (generates) a digital code corresponding to strength of the analog signal at various time instances (samples) as output. In an embodiment, the digital code equals (Vi*2n/Vref), wherein Vi represents the voltage of the input sample, Vref the reference voltage, * and / representing the multiplication and division operations respectively.
Thus, ideally Vref provided to the ADC should be constant such that the digital codes are linearly proportionate to the voltage level of the input samples. A deviation of the reference voltage from such constant value leads to corresponding errors in the digital codes. An example ADC needing a constant reference voltage is described with reference to FIG. 1 below.
FIG. 1 is a block diagram of a pipe line ADC in one embodiment illustrating the need for a constant reference voltage. ADC 100 is shown containing sample and hold amplifier (SHA) 110, stages 120-1 through 120-S, digital error correction block 130 and reference buffer 150. Each block is described below in further detail.
Reference buffer 150 generates a reference voltage (Vref) on path 152 typically from a constant DC reference voltage (e.g., bandgap reference voltage, well known in the relevant arts). The reference voltage can be in differential and/or single ended form depending on the requirements of the other components using the voltage. In order to avoid obscuring the features of the present invention, the description henceforth is provided with reference to single ended implementations. The extension of the approaches to differential circuits will be apparent to one skilled in the relevant arts by reading the disclosure provided herein, and such implementations are contemplated to be covered by various aspects of the present invention.
SHA 110 samples the input analog signal received on path 101 and holds the voltage level of the sample on path 111 for further processing. Digital error correction block 130 receives sub-codes from various stages (on paths 123-1 through 123-S respectively), and generates a digital code corresponding to the sample received on path 101. Various error correction approaches, well known in the relevant arts, may be used to correct any errors in the received sub-codes. The generated digital code is provided on path 139 as a final digital code corresponding to the voltage of a sample on the input analog signal at a particular time instant.
Each stage 120-1 through 120-S generates a sub-code (based on the reference signal Vref received on path 152) corresponding to a voltage level of an analog signal received as an input, and an amplified residue signal as an input to a (any) next stage. For example, stage 120-1 converts a voltage level on path 111 to generate a sub-code on path 123-1, and the amplified residue signal generated on path 112 is provided as an input to stage 120-2. A common reference signal Vref is provided to stages 120-1 through 120-S. FIG. 2 further illustrates (logical) components contained in each stage (described with reference to stage 120-1 only, for conciseness) of a pipe line ADC according to a known approach.
With respect to FIG. 2, stage 120-1 is shown containing flash ADC 250, digital to analog converter (DAC) 260, subtractor 270 and gain amplifier 280. Flash ADC 250 (an example of a sub ADC) converts a sample of an analog signal received on path 111 into a corresponding p-bit sub-code provided on path 256 (contained in path 123-1 of FIG. 1, and P is less than N). DAC 260 converts the sub-code received on path 256 into corresponding analog signal (Vdac) on path 267.
Subtractor 270 generates a residue signal as the difference of sample 111 (Vi) and the analog signal received on path 267. Gain amplifier 280 amplifies the residue signal (Vi−Vdac) and is provided on path 112 as an amplified residue signal. The signal on path 112 is used to resolve the remaining bits in the N-bit digital code by the subsequent stages of the ADC. The manner in which the residue signal is generated by each stage is described below with respect to FIGS. 3A and 3B.
FIG. 3A is a circuit diagram illustrating the manner in which DAC 260, subtractor 270, and gain amplifier 280 are implemented in an embodiment providing p-bit sub-codes and FIG. 3B is a timing diagram used to illustrate the sample and hold phases of the circuit. The circuit diagram is shown containing op-amp 350, feedback capacitor 360, feedback switch 380 and circuit portions 301-1 through 301-2n. Circuit portions 301-1 is shown containing sampling capacitor 330-1, switch 310A-1, 310B-land 310C-1. The remaining circuit portions 310-2 through 310-2n may also contain similar components, and are not described in the interest of conciseness. Each component is described below in further details.
The circuit in FIG. 3A operates using two phase signals, shown as sampling phase 370 and hold phase 390. In the first phase (sampling phase 370) switches 310A-1 through 310A-2n are closed at time points 371 and the remaining switches 380, 310B-1 through 310B-2n, and 310C-1 through 310C-2n are kept open. As a result, each sampling (input) capacitor 330-1 through 330-2n is ideally charged (in duration between 371–372) to the voltage of input sample received on path 111 by time point 372.
In the second phase (between durations 391–392), feedback switch 380 is closed and switches 310A-1 through 310A-2n are kept open. Connections of switches 310B-1 through 310B-2, and 310C-1 through 310C-2n are made such that the input terminals of each sampling capacitors 330-1 through 330-2n is connected either to Vref or to REFCM terminal, as determined from the output of flash ADC 250. As a result, capacitors 330-1 through 330-2n transfers a charge proportional to the difference (residue) of input signal and the Vref or REFCM to feedback capacitor 360 (up to time point 392). The residue is amplified by op-amp 350 and provided as amplified residue signal to the next stage, as desired.
However, the reference voltage Vref (on path 152) provided by reference buffer 150 may not remain constant (across stages while processing the same sample, and also while processing different samples) due to variation in the load offered by the circuit of FIG. 3A. Such a variation of the reference voltage Vref causes an error in the residue signal and/or quantization, resulting in error in the sub-codes generated by various stages.
Therefore, what is needed is a method and apparatus which at least reduces the variation in reference voltage even when the offered (e.g., by the circuit of FIG. 3A in the above example) load varies dynamically.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit (s) in the corresponding reference number.